Current Issue : January-March Volume : 2023 Issue Number : 1 Articles : 5 Articles
This brief presents an analog front-end (AFE) for the detection of electroencephalogram (EEG) signals. The AFE is composed of four sections, chopper-stabilized amplifiers, ripple suppression circuit, RRAM-based lowpass FIR filter, and 8-bit SAR ADC. This is the first time that an RRAM-based lowpass FIR filter has been introduced in an EEG AFE, where the bio-plausible characteristics of RRAM are utilized to analyze signals in the analog domain with high efficiency. The preamp uses the symmetrical OTA structure, reducing power consumption while meeting gain requirements. The ripple suppression circuit greatly improves noise characteristics and offset voltage. The RRAM-based low-pass filter achieves a 40 Hz cutoff frequency, which is suitable for the analysis of EEG signals. The SAR ADC adopts a segmented capacitor structure, effectively reducing the capacitor switching power consumption. The chip prototype is designed in 40 nm CMOS technology. The overall power consumption is approximately 13 μW, achieving ultra-low-power operation....
In order to meet the requirements of modern portable electronics for high accuracy and low power consumption of bandgap reference circuits, a new low-voltage bandgap reference with a second-order compensated circuit at 1.8 V is proposed. It features a new self-biased fully symmetric differential operational amplifier circuit with the help of split transistors for achieving low power consumption and high accuracy; by adding a new sub-threshold compensated circuit. The results of simulation show that the temperature coefficient of the second-order circuit is 3.95 ppm/◦C in the temperature range of −40 to 125 ◦C, and the power consumption is only 7.5 μW; this meets both the requirements of high precision and low power consumption. At the same time, the output noise voltage of the design is less than 30 μV/sqrt (Hz) at a frequency of 100 Hz, and the low-frequency supply voltage rejection ratio is −103 dB@100 Hz; these are acceptable for bandgap reference circuits....
A complete comparison for 14 nm FinFET and NWFET with stacked nanowires was carried out. The electrical and thermal performances in two device structures were analyzed based on TCAD simulation results. The electro-thermal TCAD models were calibrated to data measured on 30–7 nm FinFETs and NWFETs. The full set of output electrical device parameters Ion, Io f f , SS, Vth, and maximal device temperature Tmax was discussed to achieve the optimum VLSI characteristics....
It has as of late been feasible to foster calculations for video picture handling utilizing field programmable gate arrays (FPGAs). A wide scope of video picture handling applications has been made conceivable by the FPGA’s exceptional plan. On two FPGA structures, three such calculations will be executed in FPGAs in this paper. Programming has developed less valuable in video handling as picture sizes and bit profundities have expanded. Video handling requires rapid continuous frameworks like those that are the focal point of this review. Satellite and ground-based identification frameworks create a great deal of information, which may be hard to manage. Specifically, lessening how much information to be handled by DSP frameworks guarantees that main applicable information is given to a human expert. Video handling in what is to come is probably going to depend on DSP frameworks, with minimal human mediation. Human information investigators are costly and may not be totally exact; accordingly, this is obviously invaluable....
In very large-scale integration (VLSI) circuits, a partial of energy lost leads to information loss in irreversible computing because, in conventional combinatorial circuits, each bit of information generates heat and power consumption, thus resulting in energy dissipation. When information is lost in conventional circuits, it will not be recoverable, as a result, the circuits are provided based on the reversible logic and according to reversible gates for data retrieval. Since comparators are one of the basic building blocks in digital logic design, in which they compare two numbers, the aim of this research is to design a 1-bit comparator building block based on reversible logic and implement it in the QCA with the minimum cell consumption, less occupied area, and lower latency, as well as to design it in a single layer. The proposed 1-bit reversible comparator is denser, cost-effective, and more efficient in quantum cost, power dissipation, and the main QCA parameters than that of previous works....
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